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| S3C7544/P7544 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW OVERVIEW The S3C7544 single-chip CMOS microcontroller is designed for high-performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With a versatile 8-bit timer/counter and a D/A converter, the S3C7544 offers an excellent design solution for a wide variety of telecommunication applications. Up to 17 pins of the 24-pin SDIP package can be dedicated to I/O. Four vectored interrupts provide fast response to internal and external events. In addition, the S3C7544's advanced CMOS technology has realized substantially lower power consumption with a wide operating voltage range -- all at a substantially lower cost. OTP The S3C7544 microcontroller is also available in OTP (One Time Programmable) version, S3P7544. S3P7544 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P7544 is comparable to S3C7544, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C7544/P7544 FEATURES SUMMARY Memory * * 512 x 4-bit RAM 4096 x 8-bit ROM Bit Sequential Carrier * Supports 16-bit serial data transfer in arbitrary format I/O Pins * 17 pins I/O * N-channel open-drain I/O: 8 pins 8-Bit Basic Timer * * Programmable interval timer Watchdog timer Power-Down Modes * * Idle mode (only CPU clock stops) Stop mode (system clock stops) Oscillation Sources * * * Crystal, or ceramic for system clock Crystal, ceramic: 0.4-6.0 MHz CPU clock divider circuit (by 4, 8, or 64) Interval 8-Bit Timer/Counter * * * Programmable interval timer External event counter function Timer/counter clock output to TCLO0 pin Instruction Execution Times * * 0.95, 1.91, and 15.3 s at 4.19 MHz 0.67, 1.33, 10.7 s at 6.0 MHz Buzzer Output * Four frequency output to BUZ pin Operating Temperature * - 40 C to 85 C D/A Converter * 8-bit D/A converter Operating Voltage Range * * 1.8 V to 5.5 V (at 3 MHz) 2.7 V to 5.5 V (at 6 MHz) Interrupts * * * Two external interrupt vectors Two internal interrupt vectors One quasi-interrupt Package Types * * 24-pin SOP-375 24-pin SDIP-300 Memory-Mapped I/O Structure * Data memory bank 15 1-2 S3C7544/P7544 PRODUCT OVERVIEW BLOCK DIAGRAM Watchdog Timer INT0, INT1 8-bit Timer/ Counter RESET XIN XOUT Basic Timer Interrupt Control Block Clock Stack Pointer Buzzer Program Counter I/O Port 0 Program Status Word P0.0/INT0 P0.1/INT1 P0.2/KS0 P0.3/KS1 P1.0/TCL0 P1.1/TCLO0 P1.2/CLO P1.3/BUZ P2.0 DAO D/A Converter Internal Interrupts P4.0-P4.3 P5.0-P5.3 I/O Port 4 Instruction Decoder I/O Port 5 Arithmetic Logic Unit I/O Port 1 Flags I/O Port 2 512 x 4-bit Data Memory 4 K byte Program Memory Figure 1-1. S3C7544 Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C7544/P7544 PIN ASSIGNMENTS VSS XOUT XIN TEST P0.0/INT0 DAO P0.1/INT1 RESET P0.2/KS0 P0.3/KS1 P1.0/TCL0 P1.1/TCLO0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD P5.3 P5.2 P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 P2.0 P1.3/BUZ P1.2/CLO Figure 1-2. S3C7544 Pin Assignment Diagrams 24 SOP-375 24 SDIP-300 S3C7544 1-4 S3C7544/P7544 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C7544 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 P2.0 Pin Type I Description 4-bit I/O port. 1- or 4-bit read/write and test is possible. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. Pins are individually configurable as input or output. 4-bit I/O port. 1- or 4-bit read/write and test is possible. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. Pins are individually configurable as input or output. 1-bit I/O port. 1- or 4-bit read/write and test is possible. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. 4-bit I/O port. 1- or 4-bit read/write and test is possible. Pins are individually configurable as input or output. Pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. The N-channel open drain or push-pull output can be selected by software (1-bit unit). External interrupts with rising/falling edge detection External interrupts with rising/falling edge detection Quasi-interrupt input with falling edge detection External clock input for timer/counter Timer/counter clock output CPU clock output 0.5, 1, 2, or 4 kHz frequency output at 4.19 MHz for buzzer sound 8-bit D/A converter output Main power supply Ground Reset signal Chip test input pin. Hold GND when the device is operating. Crystal, ceramic oscillator signal for system clock Share Pin INT0 INT1 KS0 KS1 TCL0 TCLO0 CLO BUZ - I/O I/O P4.0-P4.3 P5.0-P5.3 I/O - INT0 INT1 KS0 KS1 TCL0 TCLO0 CLO BUZ DAO VDD VSS RESET TEST XIN, XOUT I/O I/O I/O I/O I/O I/O I/O O - - I I - P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 - - - - - - 1-5 PRODUCT OVERVIEW S3C7544/P7544 Table 1-2. Overview of S3C7544 Pin Data SDIP Pin Numbers VSS XOUT, XIN TEST P0.0, P0.1 RESET P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 P2.0 DAO P4.0-P4.3 P5.0-P5.3 VDD Share Pins - - - INT0, INT1 - KS0 KS1 TCL0 TCLO0 CLO BUZ - - - - - I/O Type - - I I/O I I/O I/O Reset Value - - - Input - Input Input Circuit Type - - - D-4 B D-4 D-2 I/O O I/O I/O - Input Output Input Input - D-2 - E-2 E-2 - 1-6 S3C7544/P7544 PRODUCT OVERVIEW PIN CIRCUIT DIAGRAMS VDD VDD P-Channel Data IN N-Channel Output Disable P-Channel Out N-Channel Figure 1-3. Pin Circuit Type A Figure 1-5. Pin Circuit Type C VDD VDD Pull-up Resistor Pull-up Enable Data Circuit Type C P-Channel IN Schmitt Trigger Output Disable In/Out Figure 1-4. Pin Circuit Type B Figure 1-6. Pin Circuit Type D-2 1-7 PRODUCT OVERVIEW S3C7544/P7544 VDD VDD PNE VDD Pull-Up Resistor Pull-up Enable Data Output Disable Circuit Type C P-Channel Data In/Out Output Disable Resistor Enable In/Out Figure 1-7. Pin Circuit Type D-4 Figure 1-8. Pin Circuit Type E-2 1-8 S3C7544/P7544 ELECTRICAL DATA 14 OVERVIEW ELECTRICAL DATA In this section, S3C7544 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- Main system clock oscillator characteristics -- Subsystem clock oscillator characteristics -- I/O capacitance -- A.C. electrical characteristics -- Operating voltage range Miscellaneous Timing Waveforms -- A.C timing measurement point -- Clock timing measurement at Xin -- Clock timing measurement at XTin -- TCL timing -- Input timing for RESET -- Input timing for external interrupts -- Serial data transfer timing Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request 14-1 ELECTRICAL DATA S3C7544/P7544 Table 14-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL All I/O ports - One I/O port active All I/O ports active Output Current Low One I/O port active Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 -5 - 35 + 30 (peak) + 15 (note) All I/O ports active Operating Temperature Storage Temperature TA Tstg - - Duty . Units V V V mA mA + 100 (peak) + 60 (note) - 40 to + 85 - 65 to + 150 C C NOTE: The values for output current low (IOL) are calculated as peak value x Table 14-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Conditions All input pins except VIH2-VIH3 P0 and RESET XIN and XOUT All input pins except VIH2-VIH3 P0 and RESET XIN and XOUT Min 0.7 VDD 0.8 VDD VDD - 0.1 - Typ - - - - Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 V Units V 14-2 S3C7544/P7544 ELECTRICAL DATA Table 14-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output High Voltage Output Low Voltage Symbol VOH VOL1 Conditions VDD = 4.5 V to 5.5 V IOH = - 1 mA VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4, 5 VDD = 1.8 V to 5.5 V IOL = 1.6 mA VOL2 VDD = 4.5V to 5.5 V IOL = 4 mA All out ports except ports 4, 5 VDD = 1.8 V to 5.5 V IOL = 1.6 mA Input High Leakage Current ILIH1 VIN = VDD All input pins except XIN and XOUT VIN = VDD XIN and XOUT VIN = 0 V All input pins except XIN, XOUT and RESET ILIL2 Output High Leakage Current Output Low Leakage Current Pull-up Resistor ILOH VIN = 0 V XIN and XOUT VO = VDD All output pins VO = 0 V All output pins RL1 VDD = 5 V; VI = 0 V except RESET VDD = 3 V RL2 VDD = 5 V; VI = 0 V; RESET VDD = 3 V 25 50 100 200 45 90 220 450 100 200 400 800 k - - - 20 3 A - - - - 0.6 3 A 0.4 2 - - 2 V Min VDD - 1.0 Typ - Max - Units V ILIH2 Input Low Leakage Current ILIL1 20 -3 A ILOL - - -3 A 14-3 ELECTRICAL DATA S3C7544/P7544 Table 14-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (DAC on) IDD2 (DAC off) Conditions Run mode; VDD = 5.0 V 10% Crystal oscillator; C1 = C2 = 22pF Run mode; VDD = 5.0 V 10% Crystal oscillator; C1 = C2 = 22pF VDD = 3 V 10% IDD3 Idle mode; VDD = 5.0 V 10% Crystal oscillator; C1 = C2 = 22pF VDD = 3 V 10% IDD4 Stop mode; VDD = 5.0 V 10% Stop mode; VDD = 3.0 V 10% 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz - - - Min - Typ 3.4 2.7 2.3 1.7 1.1 0.8 0.7 0.5 0.3 0.2 0.2 0.1 Max 10.0 8.0 8.0 5.5 4.0 3.0 2.5 1.8 1.5 1.0 3.0 2.0 A mA mA Units mA NOTES: 1. D.C. electrical values for supply current (IDD1 to IDD3) do not include the current drawn through internal pull-up 2. resistors. IDD1 typical values are measured when DADATA register value is 055H. Main Osc. Freq. CPU CLOCK 1.5 MHz 6 MHz 0.75 MHz 3 MHz 15.625 kHz 1 1.8 400 kHz 2 2.7 3 4 5 6 7 SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 14-1. Standard Operating Voltage Range 14-4 S3C7544/P7544 ELECTRICAL DATA Table 14-3. Oscillators Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration Xin Xout Parameter Oscillation frequency (1) Test Condition VDD = 2.7 V to 5.5 V Min 0.4 Typ - Max 6.0 Units MHz C1 C2 VDD = 1.8 V to 5.5 V Stabilization time (2) Crystal Oscillator Xin Xout 0.4 - 0.4 - - - 3 4 6.0 ms MHz VDD = 3.0 V VDD = 2.7 V to 5.5 V Oscillation frequency (1) C1 C2 VDD = 1.8 V to 5.5 V Stabilization time (2) External Clock Xin Xout 0.4 - 0.4 - - - 3 10 6.0 ms MHz VDD = 3.0 V VDD = 2.7 V to 5.5 V XIN input frequency (1) VDD = 1.8 V to 5.5 V XIN input high and low level width (tXH, tXL) - 0.4 83.3 - - 3 1250 ns NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 14-5 ELECTRICAL DATA S3C7544/P7544 Table 14-4. Recommended Oscillator Constants (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Manufacturer Series Number (1) FCR FCR CCR M5 MC5 MC3 Frequency Range Load Cap (pF) C1 TDK 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 3.58 MHz-6.0 MHz 33 (2) Oscillator Voltage Range (V) MIN 2.0 2.0 2.0 MAX 5.5 5.5 5.5 Remarks C2 33 (2) Leaded Type On-chip C Leaded Type On-chip C SMD Type (3) (3) NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in. Table 14-5. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - Typ - Max 15 15 15 Units pF pF pF Table 14-6. D/A Converter Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 3.5 V to 5.5 V, VSS = 0 V) Parameter Resolution Absolute Accuracy Differential Linearity Error Setup Time Output Resistance Symbol - - DLE tsu RO Condition - Min - -3 -1 - 4.5 Typ - - - - 5 Max 8 3 1 5 5.5 Units bits LSB LSB s K 14-6 S3C7544/P7544 ELECTRICAL DATA Table 14-7. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0 Input Frequency f TI VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0 Input High, Low Width tTIH, tTIL VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V Interrupt Input High, Low Width RESET Input Low Width tINTH, tINTL tRSL INT0, INT1, KS0-KS1 Input 0.48 1.8 10 - - - - 10 s s - Min 0.67 1.33 0 - 1.5 1 - MHz MHz s Typ - Max 64 Units s Table 14-8. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 1.8 V - Released by RESET Released by interrupt Min 1.8 - 0 - - Typ - 0.1 - 217/fx (2) Max 5.5 10 - - - Unit V A s ms ms NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay the execution of CPU instructions during the wait time. 14-7 ELECTRICAL DATA S3C7544/P7544 TIMING WAVEFORMS INTERNAL RESET OPERATION STOP MODE DATA RETENTION MODE VDD IDLE MODE OPERATING MODE ~ ~ V DDDR RESET EXECUTION OF STOP INSTRUCTION tWAIT t SREL Figure 14-2. Stop Mode Release Timing When Initiated by RESET IDLE MODE STOP MODE DATA RETENTION VDD NORMAL OPERATING MODE ~ ~ VDDDR EXECUTION OF STOP INSTRUCTION tSREL POWER-DOWN MODE TERMINATING (INTERRUPT REQUEST) t WAIT Figure 14-3. Stop Mode Release Timing When Initiated by Interrupt Request 14-8 S3C7544/P7544 ELECTRICAL DATA 0.8 V DD 0.2 V DD MEASUREMENT POINTS 0.8 VDD 0.2 VDD Figure 14-4. A.C. Timing Measurement Points (Except for XIN) 1/f x tXL t XH XIN VDD - 0.1 V 0.1 V Figure 14-5. Clock Timing Measurement at XIN 14-9 ELECTRICAL DATA S3C7544/P7544 1 / f TI tTIL tTIH TCL 0.7 V DD 0.3 V DD Figure 14-6. TCL Timing tRSL RESET 0.2 V DD Figure 14-7. Input Timing for RESET Signal tINTL t INTH INT0, 1 KS0 to KS1 0.8 VDD 0.2 V DD Figure 14-8. Input Timing for External Interrupts 14-10 S3C7544/P7544 MECHANICAL DATA 15 -- Pad diagram 30 8.94 0.2 MECHANICAL DATA This section contains the following information about the device package: -- Package dimensions in millimeters -- Pad/pin coordinate data table 16 0 ~ 15 30-SDIP-400 #1 15 0.25 +0.1 - 0.0 5 3.81 0.2 (1.30) 0.56 0.1 1.12 0.1 1.778 NOTE: Typical dimensions are in millimeters. Figure 15-1. 30-SDIP-400 Package Dimensions 3.30 0.3 0.51MIN 5.08MAX 27.48 0.2 10.16 15-1 S3C7544/P7544 S3P7544 OTP 16 OVERVIEW S3P7544 OTP The S3P7544 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7544 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P7544 is fully compatible with the S3C7544, both in function and in pin configuration. Because of its simple programming requirements, the S3P7544 is ideal for use as an evaluation chip for the S3C7544. VSS/VSS XOUT XIN VPP/TEST P0.0/INT0 DAO P0.1/INT1 RESET /RESET P0.2/KS0 P0.3/KS1 P1.0/TCL0 P1.1/TCLO0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD /VDD P5.3/ SCLK P5.2/ SDAT P5.1 P5.0 P4.3 P4.2 P4.1 P4.0 P2.0 P1.3/BUZ P1.2/CLO Figure 16-1. S3P7544 Pin Assignments (24 SOP-375, 24 SDIP-300 Package) 24 SOP-375 24 SDIP-300 S3P7544 16-1 S3P7544 OTP S3C7544/P7544 Table 16-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P5.2 Pin Name SDAT Pin No. 22 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input / push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Hold GND when OTP is operating. Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming. P5.3 TEST SCLK TEST 23 4 I/O I RESET VDD/VSS RESET VDD/VSS 8 24/1 I - NOTE: ( ) means the 32-SOP OTP pin number. Table 16-2. Comparison of S3P7544 and S3C7544 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability S3P7544 4 K-byte EPROM 1.8 V (3 MHz) to 5.5 V VDD = 5 V, VPP (TEST) = 12.5 V 24 SOP, 24 SDIP User Program one time S3C7544 4 K-byte mask ROM 1.8 V (3 MHz) to 5.5 V - 24 SOP, 24 SDIP Programmed at the factory OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P7544, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below. Table 16-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/ MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode NOTE: "0" means Low level; "1" means High level. 16-2 S3C7544/P7544 S3P7544 OTP OTP ELECTRICAL DATA Table 16-4. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO I OH I OL All I/O ports - One I/O port active All I/O ports active Output Current Low One I/O port active Conditions - Rating - 0.3 to + 6.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 -5 - 35 + 30 (peak) + 15 (note) All I/O ports active Operating Temperature Storage Temperature TA Tstg - - Duty . Units V V V mA mA + 100 (peak) + 60 (note) - 40 to + 85 - 65 to + 150 C C NOTE: The values for output current low (IOL) are calculated as peak value x Table 16-5. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Input High Voltage Symbol VIH1 VIH2 VIH3 Input Low Voltage VIL1 VIL2 VIL3 Conditions All input pins except VIH2-VIH3 P0 and RESET XIN and XOUT All input pins except VIH2-VIH3 P0 and RESET XIN and XOUT Min 0.7 VDD 0.8 VDD VDD - 0.1 - Typ - - - - Max VDD VDD VDD 0.3 VDD 0.2 VDD 0.1 V Units V 16-3 S3P7544 OTP S3C7544/P7544 Table 16-5. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Output High Voltage Output Low Voltage Symbol VOH VOL1 Conditions VDD = 4.5 V to 5.5 V IOH = - 1 mA VDD = 4.5 V to 5.5 V IOL = 15 mA Ports 4, 5 VDD = 1.8 V to 5.5 V IOL = 1.6 mA VOL2 VDD = 4.5V to 5.5 V IOL = 4 mA All out ports except ports 4, 5 VDD = 1.8 V to 5.5 V IOL = 1.6 mA Input High Leakage Current ILIH1 VIN = VDD All input pins except XIN and XOUT VIN = VDD XIN and XOUT VIN = 0 V All input pins except XIN, XOUT and RESET ILIL2 Output High Leakage Current Output Low Leakage Current Pull-up Resistor ILOH VIN = 0 V XIN and XOUT VO = VDD All output pins VO = 0 V All output pins RL1 VDD = 5 V; VI = 0 V except RESET VDD = 3 V RL2 VDD = 5 V; VI = 0 V; RESET VDD = 3 V 25 50 100 200 50 100 250 500 100 200 400 800 k - - - 20 3 A - - - - 0.6 3 A 0.4 2 - - 2 V Min VDD - 1.0 Typ - Max - Units V ILIH2 Input Low Leakage Current ILIL1 20 -3 A ILOL - - -3 A 16-4 S3C7544/P7544 S3P7544 OTP Table 16-5. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Supply Current (1) Symbol IDD1 (DAC on) IDD2 (DAC off) Conditions Run mode; VDD = 5.0 V 10% Crystal oscillator; C1 = C2 = 22pF Run mode; VDD = 5.0 V 10% Crystal oscillator; C1 = C2 = 22pF VDD = 3 V 10% IDD3 Idle mode; VDD = 5.0 V 10% Crystal oscillator; C1 = C2 = 22pF VDD = 3 V 10% IDD4 Stop mode; VDD = 5.0 V 10% Stop mode; VDD = 3.0 V 10% 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz 6.0MHz 4.19MHz - - - Min - Typ 3.4 2.7 2.3 1.7 1.1 0.8 0.7 0.5 0.3 0.2 0.2 0.1 Max 10.0 8.0 8.0 5.5 4.0 3.0 2.5 1.8 1.5 1.0 3.0 2.0 A mA mA Units mA NOTES: 1. D.C. electrical values for supply current (IDD1 to IDD3) do not include the current drawn through internal pull-up 2. resistors. IDD1 typical values are measured when DADATA register value is 055H . Main Osc. Freq. CPU CLOCK 1.5 MHz 6 MHz 0.75 MHz 3 MHz 15.625 kHz 1 1.8 400 kHz 2 2.7 3 4 5 6 7 SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8 or 64) Figure 16-2. Standard Operating Voltage Range 16-5 S3P7544 OTP S3C7544/P7544 Table 16-6. Oscillators Characteristics (TA = - 40 C + 85 C, VDD = 1.8 V to 5.5 V) Oscillator Ceramic Oscillator Clock Configuration Xin Xout Parameter Oscillation frequency (1) Test Condition VDD = 2.7 V to 5.5 V Min 0.4 Typ - Max 6.0 Units MHz C1 C2 VDD = 1.8 V to 5.5 V Stabilization time (2) Crystal Oscillator Xin Xout 0.4 - 0.4 - - - 3 4 6.0 ms MHz VDD = 3.0 V VDD = 2.7 V to 5.5 V Oscillation frequency (1) C1 C2 VDD = 1.8 V to 5.5 V Stabilization time (2) External Clock Xin Xout 0.4 - 0.4 - - - 3 10 6.0 ms MHz VDD = 3.0 V VDD = 2.7 V to 5.5 V XIN input frequency (1) VDD = 1.8 V to 5.5 V XIN input high and low level width (tXH, tXL) - 0.4 83.3 - - 3 1250 ns NOTES: 1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated. 16-6 S3C7544/P7544 S3P7544 OTP Table 16-7. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - Typ - Max 15 15 15 Units pF pF pF Table 16-8. Comparator Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 3.5 V to 5.5 V, VSS = 0 V) Parameter Resolution Absolute Accuracy Differential Linearity Error Setup Time Output Resistance Symbol - - DLE tsu RO Condition - Min - -3 -1 - 4.5 Typ - - - - 5 Max 8 3 1 5 5.5 Units bits LSB LSB s K Table 16-9. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 1.8 V to 5.5 V) Parameter Instruction Cycle Time Symbol tCY Conditions VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0 Input Frequency f TI VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V TCL0 Input High, Low Width tTIH, tTIL VDD = 2.7 V to 5.5 V VDD = 1.8 V to 5.5 V Interrupt Input High, Low Width RESET Input Low Width tINTH, tINTL tRSL INT0, INT1, KS0-KS1 Input 0.48 1.8 10 - - - - 10 s s - Min 0.67 1.33 0 - 1.5 1 - MHz MHz s Typ - Max 64 Units s 16-7 S3P7544 OTP S3C7544/P7544 Table 16-10. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 1.8 V - Released by RESET Released by interrupt Min 1.8 - 0 - - Typ - 0.1 - 217/fx (2) Max 5.5 10 - - - Unit V A s ms ms NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay the execution of CPU instructions during the wait time. 16-8 |
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